.include "m16def.inc"
Ldi r16, 0XFF
.def temp = r16
out DDRA, r16

         ldi temp, LOW(RAMEND)             ; LOW-Byte der obersten RAM-Adresse
         out SPL, temp
         ldi temp, HIGH(RAMEND)            ; HIGH-Byte der obersten RAM-Adresse
         out SPH, temp
call Verzoegerung
ldi r16,0

; start
ldi r16, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)
out TWCR, r16

;Auf Start warten
wait1:
in r16,TWCR
sbrs r16,TWINT
rjmp wait1

; Korr Ablauf prüfen
in r16,TWSR
andi r16, 0xF8
cpi r16, 0x08; 0x08  =START
brne ERROR

; Adresse + Schreibbit

ldi r16, 0b10011110
out TWDR, r16
ldi r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16

; Warten auf das Versenden der Addresse

wait2:
in r16,TWCR
sbrs r16,TWINT
rjmp wait2

; Testen auf erfolgreiches Versenden

in r16,TWSR
andi r16, 0xF8
cpi r16, 0x18
brne ERROR

; Senden des Pointers
ldi r16, 0
out TWDR, r16
ldi r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16

; Auf Sendevorgang Warten

wait3:
in r16,TWCR
sbrs r16,TWINT
rjmp wait3

; Sendevorgang Testen

in r16,TWSR
andi r16, 0xF8
cpi r16, $28
brne ERROR

; Rp Start

ldi r16, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)
out TWCR, r16

; Warten Rp Start

RPwait1:
in r16,TWCR
sbrs r16,TWINT
rjmp RPwait1

; Test Rp Start

in r16,TWSR
andi r16, 0xF8
cpi r16, 0x10 ; RP Start
brne ERROR

; Adresse + RBit Schreiben

ldi r16, 0b10011111
out TWDR, r16
ldi r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16
; Warten auf Adresse + RBit Schreiben
RPwait2:
in r16,TWCR
sbrs r16,TWINT
rjmp RPwait2
; Testen Adresse + RBit Schreiben

in r16,TWSR
andi r16, 0xF8
cpi r16, 0x40
brne ERROR
; Warten auf Daten

RPwait3:
in r16,TWCR
sbrs r16,TWINT
rjmp RPwait3

in r20, TWDR





Write:  SBIC  EECR,EEWE
  RJMP  Write
  LDI  r16,0
        LDI     r17,0
  OUT  EEARH,r16
        OUT     EEARL,r17
  OUT  EEDR,r20
  SBI  EECR,EEMWE
  SBI  EECR,EEWE


ldi r16, 0b11110000
out PortA, r16

end:
jmp end

ERROR:
ldi r16, 0b00100000
out PortA, r16
Errorend:
jmp Errorend

Verzoegerung:
push r16
push r17
push r18

ldi r16,20
Schlr16:

	ldi r17,255
	Schlr17:
	
		ldi r18,255
		Schlr18:
	
			nop
		
		dec r18
		BRNE Schlr18
	
	dec r17
	BRNE Schlr17
	
dec r16
BRNE Schlr16

pop r18
pop r17
pop r16
ret